As is well known, a non-volatile memory is able to continuously retain data after the supplied power is interrupted. A flash memory is one of the most popular non-volatile memories. Generally, each storage cell of the flash memory has a floating gate transistor. The storing status of the floating gate transistor may be determined according to the amount of the stored charges.
Recently, a novel non-volatile memory with a resistive element as the main storage element has been introduced into the market. This non-volatile memory is also referred as a resistive random access memory (RRAM).
FIG. 1 is a schematic cross-sectional view illustrating a conventional non-volatile memory with a resistive element. This non-volatile memory is disclosed in U.S. Pat. No. 8,107,274 for example. As shown in FIG. 1, the non-volatile memory 300 has a (1T+1R) cell. The term “1T” denotes one transistor. The term “1R” denotes one resistor. That is, the non-volatile memory 300 comprises a transistor 310 and a resistive element 320. The resistive element 320 is connected to the transistor 310. In addition, the resistive element 320 is a variable and reversible resistive element, and the transistor 310 is a switch transistor. When the transistor 310 is turned on, the resistive element 320 may be programmed or the storing status of the resistive element 320 may be read.
The transistor 310 comprises a substrate 318, a gate dielectric layer 313, a gate electrode 312, a first source/drain region 314, a second source/drain region 316, and a spacer 319. The substrate 318 may be a well region.
The resistive element 320 comprises a transition metal oxide layer 110, a dielectric layer 150, and a conductive plug module 130. The dielectric layer 150 is formed on the first source/drain region 314. The conductive plug module 130 is disposed on the transition metal oxide layer 110.
The conductive plug module 130 comprises a metal plug 132 and a barrier layer 134. The metal plug 132 is vertically disposed over the transition metal oxide layer 110, and electrically connected with the transition metal oxide layer 110. The barrier layer 134 is arranged around the metal plug 132. The transition metal oxide layer 110 is formed by reacting a portion of the dielectric layer 150 with the barrier layer 134. Moreover, the resistance values of the transition metal oxide layer 110 in a set status and a reset status are different. Each of the resistance values is correlated with a corresponding storing status. Consequently, the transition metal oxide layer 110 has the memory function.
FIGS. 2A˜2D schematically illustrate a method of manufacturing a conventional non-volatile memory. As shown in FIG. 2A, a transistor is provided. For clarification and brevity, the procedures of fabricating the transistor are not described herein. The transistor comprises a gate electrode 312, a first source/drain region 314, and a second source/drain region 316. Moreover, a gate dielectric layer 313 is formed on the substrate 318 (or the well region), and a gate electrode 312 is formed on the gate dielectric layer 313. The first source/drain region 314 and the second source/drain region 316 are formed in the substrate 318 (or the well region), and located at two opposite side with respect to the gate electrode 312. The spacer 391 is located at the sidewall of the gate electrode 312. Moreover, the dielectric layer 150 is formed on the first source/drain region 314. An interlayer insulating layer 160 is formed on the dielectric layer 150 and the transistor.
Then, as shown in FIG. 2B, an etching process is performed to form an opening 162 in the interlayer insulating layer 160 and a part of the dielectric layer 150. Meanwhile, the remaining dielectric layer 150 is arranged between a bottom 152 of the opening 162 and the first source/drain region 314.
Then, as shown in FIG. 2C, a barrier layer 134 is formed on an inner wall and the bottom 152 of the opening 162.
As shown in FIG. 2D, the barrier layer 134 at the bottom 152 of the opening 162 and the dielectric layer 150 are contacted and reacted with each other to produce a transition metal oxide layer 110. After the transition metal oxide layer 110 is formed, a part of the dielectric layer 150 is still arranged between the transition metal oxide layer 110 and the first source/drain region 314. Moreover, a metal plug 132 is filled into the opening 162. The metal plug 132 is electrically connected with the transition metal oxide layer 110.
However, it is difficult to control the etching process of the opening 162. Consequently, the thickness of the remaining dielectric layer 150 at the bottom 152 of the opening 162 cannot be precisely controlled. Under this circumstance, the resistance value of the transition metal oxide layer 110 after the reaction is usually inconsistent. In other words, it is difficult to produce the (1T+1R) cells of the conventional non-volatile memory on large scale.